One can simulate a hardware design once it is completed – either as a schematic one or on HDL. Simulation is normally done to gain confidence that it will work properly before actually running in an FPGA. All that is required for Simulation is a form of input stimulus which the FPGA Simulator software could determine to indicate the respective outputs. By using an Interactive waveform editor, entering the shapes of the inputs (with a few clicks of computer mouse) the simulator software draws the shapes of the outputs. It is simple for the beginners to understand and gain confidence in simulation procedure. The test-bench method involves a non-synthesizable HDL design which will create stimulus for another design – which normally is synthesizable one. This is a far more dependable and powerful one.